Many data processing systems contains a memory controller, which is an electronic component that assists a processor to interface with random access memory (RAM) devices. Typically, a memory controller controls a number of address lines, which defines the maximum amount of addressable memory. In order to make sure that the memory controller works properly, the full addressing capacity need to be tested. In conventional testing, the memory controller is connected to memory devices that span the maximum addressable memory. This allows the testing of the full addressing capacity.
In advanced systems, the amount of addressable memory is large. In some situations, it may be very difficult to have memory devices that occupy the full span. One example of such a situation can be found in system-on-a-chip (SoC) devices that contain a processor, memory, and input-output peripherals. The amount of physical memory in the SoC is generally much less than the maximum addressable memory of the processor. Even though it may be possible to attach external memory devices to the SoC, it is desirable to conduct all testing within the SoC.
Consequently, there is a need for a new method of testing that does not requires large amount of memory.